1. Field of the Invention
The present invention relates to a method of selective chemical vapor deposition for forming thin films and an apparatus for carrying out the selective chemical vapor deposition, and particularly to chemical vapor deposition of semiconductor single-crystal films at mask opening portions in mask-patterned substrates to be processed.
2. Description of the Prior Art
Development of IC is (Integrated Circuit) using compound semiconductors having excellent characteristics on high-speed processes has been actively advanced accompanying increase of information amount. Currently, the gate length of GaAs MOSFET IC which is one of the main elements of the compound semiconductor IC has about 1 .mu.m rule in products.
However, it is necessary to realize elements having better characteristics than the present level such that with the gate length controlling the short channel effect, the parasitic resistance and capacitance should be reduced.
With respect to means of solving these problems, there has been the report on test preparation of a MOSFET LSI having construction in which a source portion 1 and a drain portion 2 are respectively formed in layers as shown in FIG. 2 by a selective chemical vapor deposition method, that is, an organometallic chemical vapor deposition (MOCVD) method (which was reported in Technical Report of Electronic Communication Society ED88-82, P-29, Haga et al.).
By using the MOCVD method, impurity diffusion in the horizontal direction can be reduced around the gate and the short channel effect can be controlled as compared with an LSI of a conventional construction as shown in FIG. 1. Moreover, since the contact regions to electrodes are formed by the so-called epitaxial growth method, it is possible to carry out high density doping therein, thus the parasitic resistance of the regions can be reduced.
However, in the selective chemical vapor deposition method by such a conventional MOCVD method, since the growth rate greatly depends on the ratio of the area (S) and the peripheral length (L) of an opening portion, in other words, the ratio of the area of the opening portion consisting of GaAs and the area of the masking member or the gate member, it is very difficult to control the film thickness uniformly over all openings on the substrate.
Further, there is the problem that the range of the growth condition so as to suppress the generation of polycrystalline particles on the mask portion et al. is relatively narrow.
To solve these problems in the prior art, for example, a dummy pattern is arranged on each region of a relatively wide mask portion in a mask pattern to control the film thickness uniform by adjusting constantly the ratio of the areas of growth portions and mask portions all over the substrate.
However, by arranging the dummy pattern, capacitance of wiring provided on the N.sup.+ GaAs layer formed on a semi-insulating substrate is so increased that the required high-speed characteristic can not be obtained.
Furthermore, to control the deposition of such polycrystalline particles on the mask member and the like even when the dummy pattern is provided, the ratio of the supply amount between a Group III and a Group V materials, pressure and temperature for the growth must be precisely controlled. In such a case, it is very difficult to obtain a wide margin on the growth condition, thus the productivity can not be increased to a desirable level.
Moreover, in the selective chemical vapor deposition method based on such conventional MOCVD method, as designated by some arrows in FIG. 3, the thickness of the grown film in boundary regions between the mask portions and GaAs becomes larger than that of other regions thereof. This phenomenon is likely to cause breaking of metal wiring formed on the regions.
These problems are related to the selective chemical vapor deposition on processed substrates for chemical compound semiconductors, however, these must be also considered in case of selective chemical vapor deposition for forming dielectric waveguide channels for OEIC (Optoelectric Integrated Circuit).